One of the primary enabling blocks in the silicon interface for communication networks is the clock and data recovery (“CDR”) circuit. CDR circuits compare an incoming non-return to zero (NRZ) data stream to an on-board or local clock signal using a phase detector and, based on the phase difference, adjust the clock signal until it is in-phase or aligned with the data stream. The in-phase clock signal can then be used to interpret the incoming NRZ data stream. Typically, CDR circuits employ a phase-locked loop architecture where a voltage signal proportional to the phase or frequency difference is used to adjust a voltage-controlled oscillator (VCO), which provides the local clock signal. However, the use of a VCO can introduce an undesirable amount of timing jitter.
Conventional CDR circuits also commonly use full-rate architectures, which do not allow for easy scaling to higher speeds and frequencies. This is because full-rate architectures require more system components to work at higher frequencies and this limits the maximum use of the technology capabilities. Certain half-rate structures also use a large number of current-mode logic (“CML”) logic components to design the phase detector building block, which is also difficult to replicate at higher bit rates because the current drive and voltage swing capabilities of these components at high frequencies are severely limited by technology. The necessity to combine phase detection and frequency detection to achieve a fast acquisition time and better accuracy further complicates the design of phase detectors at higher frequencies.
Furthermore, CDR circuits for high data rates, such as 40 Gigabits per second (Gb/s), have been demonstrated using Bipolar Complimentary-Metal-Oxide Semiconductor (“BiCMOS”) and compound semiconductor processes. However, these processes are expensive, power hungry and not capable of integration with the remaining communication architecture.
Accordingly, improved clock and data recovery circuits are desirable.